Our group conducts research on the design of integrated circuits for wireless communication. Conformable antennas and RF/ microwave, circuits, and systems.

We also conduct research on Biomedical implacable devices and bioinformatics. Current active projects are:

Nanoscale Antenna for

We have designed a graphene based nanoscale antenna as an engineered nanocarriers. Engineered nanoparticle has a resonant frequency and can be used for diagnostic and drug delivery. The ability of the antenna to resonate at a particular frequency will give researchers ability to communicate and control nanoparticles. Such nanocarriers can provide advance detection system and help identify toxicity of nanoparticles in the body.

BIU develops comprehensive biomedical instruments and computation tools to assist biomedical researchers to conduct, analyze and interpret experiments on a dramatically accelerated pace. BIU utilizes cloud computing and Apache Map-Reduce frameworks to process unlimited amounts of scattered data via parallel computing on large clusters of computations nodes.

The objective of the research is to fabricate a nenoantenna MOM diode system. The approach is to use nano-imprint lithography technique to print spiral antenna array. Here we present design of small spiral antenna. Arms of the spiral are fed 180 degrees out of phase, thus antenna radiates when the current in spiral are in phase. Design has been simulated in Feko and results are presented here. Nano scale design can lead to interesting and unexpected behavior we are investigating critical behavior of antenna at previously unattainable special resolution and sensitivity.

Dynamiclly Configured Memory Design

As on-chip cache size has increased considerably in recent high-performance microprocessor technologies, power dissipation and leakage current in SRAM have become critical. Sub-threshold leakage current flowing from drain to source, even when the transistor is not operating, has been a dominant leakage current in high performance microprocessors where L1 and L2 cache occupy majority of die area. As transistor size scales down, power dissipation becomes a serious problem that limits overall system performances. The objective of the research is the implementation of 64x64 multi-port Static Random Access Memory (SRAM) and newly proposed dynamically configured multi-port SRAM in 65 and 32nm process. A preliminary study conducted by our group indicates that proposed memory will reduce silicon area by 35-45% and power dissipation by nearly 50%

Vedic Logic Computing

The objective of this project is to implement high speed Vedic multiplier in VLSI. Traditionally multiplications require extensive hardware resources and processing time. We are implementing a Vedic multiplier that will increase speed and reduce power by reducing the numbers of iterations.

Conformable Antenna & RF Circuit for remote health monetoring

Phd Students Kris Erodula

Email: kerodula@bridgeport.edu •

Research Interests: Distributed Computing, Parallel processing, Cloud Computing, Bio Informatics Algorithms, Programming Lanugages, Object Oriented, Relational Design and Languages, Enterprise Service Bus, Service oriented Architectures,Information Architecture,Web Services, Open Source Frame works, Java J2EE enterprise Frameworks.

• Email: imacwan@bridgeport.edu
• Office: Tech 150, Cubicle: N
• Research Interests: Design and fabrication of analog/mixed signal VLSI chips, VLSI testing, BioMEMS, nanotechnology and biomedical engineering.

Graduate Assistants:

Yeshwanth Babu