During receive operations, the transmit sequence is reversed. The serial shift register receives data and transfers it to a parallel receive data register (SCDR) as a complete word. An advanced data recovery scheme distinguishes valid data from noise in the serial data stream. The data input is selectively sampled to detect receive data, and a majority voting circuit determines the value and integrity of each bit.
Two methods of wakeup are available: idle-line wakeup and address-mark wakeup. During idle-line wakeup, a sleeping receiver awakens as soon as the RxD line becomes idle. In the address-mark wakeup, logic one in the most significant bit (MSB) of a character wakes up all sleeping receivers. Since we are using only one chip, we use the idle-line wakeup.
Three error conditions occur during generation of SCI system interrupts. They are the SCDR overrun, received bit noise, and framing errors. Three bits (OR, NF, and FE) in the SCSR register are set to indicate that the respective error has occured. A read of the SCSR (with the respective bit set) followed by a read of the SCDR clears the bit, and ensures normal operation.