University
of Bridgeport
School of Engineering and Design
Department of Computer Science and Engineering
Standard Cell VHDL synthesis lab using Mentor-Graphics tools
Introduction
This is an advanced level tutorial. It concludes the lab excersises for
the "Introduction to VLSI" and prepares for the next labs level in the
advanced VLSI course. As this is an advanced lab, it has a few prerequisites.
First it assumes you are convenient with the tools that were already covered
in previous lab sessions, specifically,IC Station.
It also assumes you have completed all the previous lab assignments as
it builds upon them. Finally, it assumes you have the corrected set of
VHDL source files of the Up/Down counter design from the "VHDL Design tutorial".
As you will notice, this tutorial is "feeding" you with less guidelines
and data than previous ones. It expects you to be more independent and
inquisitive in your work.
In this lab you will go through a VHDL multi-file design synthesis into
a full layout ASIC which is almost ready to be fabricated. The stages you
will work through are the following:
-
Use Leonardo Spectrum to recompile/synthesize your design.
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Load the design into IC station, Auto Floorplan, and Autoroute it.
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Check DRC on the design.
Introduction to applications
In this lab, you will use one new product out of the Mentor-Graphics package.
Leonardo-Spectrum
Leonardo-Spectrum is a multi-target synthesis tool. It will take design
sources in a variety of hardware design languages, optimize the design
for either timing or area constraints, and map the design towards a specific
technology.
Lets get to work!
Compilation and Synthesis
-
Change your current directory to mentor_work
We assume that your Up-Down counter VHDL design is saved in mentor_work/UD
Start Leonardo:
Leonardo-Spectrum will start and you will be presented with the GUI. We
need to select a technology and load the library:
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Click on the Technology tab
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In the Technologies window, expand the ASIC tree, then the ADK tree, and
select the ami0.5 (typ) technology.
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Click on the "Load Library" button.
The Technology library will be loaded into the synthesizer. Now, we will
load the input files.
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Click on the Input tab
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Click on the Working Directory button, then select the UD directory as
the current working directory.
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Click on the Open files button, then select all the 4 .vhd files.
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Click on the Read button.
The compiler will read the input files and compile them. Any VHDL errors
will be flagged now. You should notice that only green and blue dots are
appearing in the log window on the top right handside of the window. Now,
we are going to optimize and map the design. By default, the synthesizer
will optimize for area and will also run timing optimization.
-
Select on the Preserve hierarchy button so that the resultant design will
keep the hierarchy information in the VHDL source.
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Click on Optimize.
The synthesizer will optimize and map the design. You can notice the "WARNING"
notices on the log window as the design is re-evaluated after failing timing
DRC requirements. Again, you should only see green and blue dots in the
log. The design is ready to be written out. You can see the actual implementation
of the design by clicking on the Tools->View Gate Level Schematic. We will
now write a netlist file that would be read back into the ICstation tool:
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Click on the Output tab.
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Change the Filename to <your_home_directory>/mentor_work/udcount.edf
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Select the Format to EDIF
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Click on the EDIF Out Options
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Select "Write out power and ground..."
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Click on Apply
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Select the bottom Output Files tab
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Click on Write
We can now close Leonardo and start with the placement tools.
Compilation and Synthesis
You should verify that you see the file udcount.edf in the mentor_work
directory. This file contains the netlist of your synthesized design in
the EDIF format. We now need to convert the file from the EDIF format to
the native Mentor design database (EDDM). The conversion can be done by
the script ediftoeddm which will convert the design and create a viewpoint
for layout:
-
type "ediftoeddm udcount"
The tools will read the EDIF database, entity by entity, and create the
parts and viewpoints. We now start the placement and routing tool ICstation.
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type ic
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Click on [Session]create
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in the cell name, type udcount
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in the attach library, type "$ADK/technology/ic/ami05"
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click on "With connectivity"
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in the EDDM Schematic Viewpoint type "$MGC_WD/udcount/udcount"
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Click on the Logic Loading options
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Select the Flat Logic Loading
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Click on OK, then again on OK
The design and libraries will be read into the tools. Please wait until
the tool will finish all the loading. We now have to floorplan the design.
Floorplanning is mapping the standard cells in the design on the silicon.
The tool is not placing any cells but rather does "wishful thinking" on
optimizing the area in placing the cells.
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Click on [IC Palettes]Floorplan
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Click on [Floorplan]Autofp
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Accept the defaults by clicking OK
The tool should floorplan the design and you should see the aproximated
cell layout (channels) being marked in bright green. We now have to place
the actual cells:
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Click on [Floorplan]P&R
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Click on [Place & Route]StdCel
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Click on OK
This will place all the standard cells in the design onto the floorplan.
You can see the actual cells on the channels. You will also note some yellow
lines extending between the cells. Those lines represent connectivity information
between the cells. Those lines are only logical connections (rat's nest).
We now need to place the ports of the design on the floorplan boundry:
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Click on [Place & Route]Ports
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Aceept the defaults and click OK
You will see more "rat's nest" lines extending to the floorplan boundries.
We will now run the auto-router to route all the logical connections using
metal layers:
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Click on [Place & Route]All
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Click OK
The auto-router will route the design and in a few seconds the design will
be fully connected. You now have a fully placed and routed design on the
silicon. The only thing left to be done is to verify the layout.
-
Run a DRC check on the design. If any errors are found, you must correct
them manually.
After your design passes DRC, you are almost set for fabrication. The only
thing left is wiring up the design into the padframe, but this is a subject
that will be covered in the advanced course. A few subjects that were not
covered in this lab:
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High effort optimization
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Timing optimization
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Critical path analysis
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Automatic Placement optimization
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Padframe inclusion
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Design backannotation
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Post layout simulation
Those subjects and more will be covered in the advanced VLSI course.