University
of BridgeportSchool of Engineering and Design
University
of Bridgeport
This tutorial will give you a short introduction to Mentor-Graphics tools and guide you through the creation of a simple NAND gate. The tutorial assumes that you are already familiar with VLSI techniques and with the AMI/Mosis tinychip design rules. Mentor Graphics is the software package you will use to create your full custom design of an IC chip. The Mentor-Graphics package is a state of the art CAD tool being used by top rated chip design companies for chip fabrication. The package is comprised out of many (more the a hundred) different applications which enable the engineer to create a fully operational fabricated product out of scratch. Because of the size and complexity of the package, it comes with a bookcase of more then 150 books!. It's obvious that this amount can't be delivered to a customer and so an on-line context-sensitive help system was developed. This system can be invoked by running "mentorhelp" on every Mentor-capable machine (all the CSE UNIX workstations) or clicking on the help item in every Mentor application. You are encouraged to get yourself familiar with the help system. It contains all of the Mentor documentation and is packed with search and hypertext-like (like a WEB page) goodies. This tutorial, your instructor and the Mentor technical assistant will not be able to assist you in every problem so you should advise regularly with the online-help.
In this course, you will use only three products out of the Mentor-Graphics
package. These are:
1. Design Architect (DA)
The Design Architect is multi-level design environment entry tool. It will
be used by you as a schematic entry tool. You will design your project
at the transistor level and enter the schematic with it.
2. Design Viewpoint Editor (DVE)
This tool is used to create a special data object called the design viewpoint.
The design viewpoint contains a subset of the project's schematic data
which is going to be used for a specific tool as the input data. Every
design you create in DA must have a unique viewpoint in order to be passed
to the next tool. The main reason for having DVE is in order to be able
to split the design algorithm into a few different branches so different
methodologies can be considered inside a single design (for example, you
can describe a single block in your design in two different ways, and create
two viewpoints for the whole design, each containing a different block
in it so the downstream applications can evaluate the design using the
two different blocks). You will probably not use DVE much. but you must
use it at least once to create an ICGraph Viewpoint (see the next application).
3. ICStation
This is the main set of programs to create the real silicon masks out of
your design. ICStation gives the designer a verity of tools to perform
the layout and verification process. You will use ICStation's ICGraph tool
to handcraft layout your silicon mask. Then you will use ICRules and ICTrace
tools to verify the correctness of your design as opposed to the technology
constraints and the schematic description of the project.
The silicon process we are going to use in all lab sessions is the C5N process by American Microsystems, Inc. (AMI). The AMI C5N is an N-Well sub-micron CMOS process. The process is for 5V VDD systems, and has 3 metal layers, 2 poly layers, and a high resistance layer. We will use only 2 metal layers (METAL1 and METAL2), and one poly. While using the process in the Mentor-Graphics tools, you will be using the Mosis Scalable-CMOS (SCMOS) design rules. The C5N process has a feature size of 0.60 micron, and uses a lambda of 0.30 micron. Remember that in ICGraph, every minor grid is 0.5 lambda. All designs must fit into a Mosis TinyChip unit which is 1.5 mm x 1.5 mm in size. Although there is no rule for a minimum channel width, Mosis and AMI recommend to use a minimum channel width of 1.8 micron (which is 6 lambda for our process).
Lets get to work!
Log into one of the Sun SPARC stations and type the following:
mentorprep
This will start a special script that will prepare your account to run
Mentor-Graphics. The script should issue a "successful" message.
If it didn't, ask for assistance from your Mentor TA. You should now log
out and log in again to make the changes effective.
1. Log into a Mentor-capable machine and start an X-windows session.
2. Open a terminal window.
3. Start DA by typing da in the terminal.
4. Resize the DA window so it will cover most of your screen.
5. Open a new sheet: [session_palette] > OPEN SHEET
6. Click at the end of the text in the Component Name box and type: /mynand
7. Click on the OK button.
You should get a clean schematic sheet.
8. Maximize the sheet window.
9. Get the first part for your design: Libraries > ADK Libraries
and in the ADK_Library palette on the right side: SDL Parts >
p-fet-4
You should see the part in the active part window and under your cursor
as you move it inside the sheet window.
10. Drop it somewhere on the sheet (click the left mouse to drop it).
You should get yourself familiar with some editing functions of DA. You
should, for example, "View > Zoom out" now to see more of
your sheet. use the Edit move and copy functions to move and replicate
parts.
11. Continue to place all the necessary parts in the NAND design so it
will look similar to figure 1.
Figure 1
12. Use the right mouse button over the palette area to get back to
the schematic_palette.
13. Click over ADD WIRE, and start connecting the parts in the design.
(remember to click on all the nodes of a net and press OK after the whole
net is connected). DonÆt forget the ports, VDD and VSS.
14. Change the Port names to your design names (A, B, Out):
Part of the information needed for fabrication is the physical dimensions
of the FET's gate region. We will now add those parameters to the schematic.
15. Unselect all (Press F2).
16. Select the transistors that have equal dimensions.
17. Press the right mouse button over the sheet window.
18. Drag to: Properties > Change > Value
19. In the dialog box, enter the word length in the Property Name, fill
the value box with the needed value, choose the Type to be number,
and finally, press OK.
20. Do 15-19 again for the width property.
Note: DO NOT! change the L and W properties. Those are pre-filled properties
required for down-stream applications. Changing them will break your design.
21. Unselect all.
22. Run a check on your sheet: Check > Sheet The Check should return
without errors
You now have a full schematic design of mynand. Save it and exit DA:
23. File > Save sheet
24. [MGC] Exit
Now we have to create a viewpoint for the mynand design.
The ADK kit has an automated script that creates all necessary viewpoints
for you automatically. The script usage is as follows:
adk_dve
To have the viewpoint editor create the viewpoints for us, type the
following:
adk_dve mynand -technology ami05
You will see a lot of text scrolling on the screen. After you get your
shell prompt back you are now ready to proceed with the actual layout
of the NAND gate.
1. Invoke ICStation by typing ic at the terminal.
Each silicon entity in Mentor-Graphics is referred to as a "Cell".
Our NAND gate is a very simple design and so will be a single cell design.
Your final project design, though, should be hierarchical and built out
of many cells. Create a new cell for the NAND gate layout:
2. Click on Create in the [Session] palette.
3. In the Cell Name fill in mynand, and select Ninety in Angle Mode. Click
OK.
A new cell window has been created for you having the name "mynand".
4. Maximize the cell window.
We now start to draw the masks. There are many editing and selection functions
available in ICGraph. At first you will have some trouble interacting with
the ICGraph user interface, but as you gain experience with it you'll appreciate
the ingenuity behind every function. There are 7 editing menus containing,
more or less, the same commands. Each one is simply targeted for different
jobs. We need a general editing menu so we should use Expert Edit (don't
be alarmed, Expert Edit is not only for experts. it has the same functions
as Edit, but it opens less "dialog boxes" and so interacts faster
with the user).
5. Click on Expert Edit in the palette.
The Expert Edit palette appears. It is divided into 4 sections. The SEL/UNSEL
sections are for selecting and unselecting objects in the cell window.
The ADD is for adding new objects, and the EDIT is for proper editing functions
(like copy, flip, move, notch and more...).
We start by selecting the active layer.
6. Click on LAY.
7. Select ACTIVE and click OK.
8. Click on SH+
9. Press the left mouse button somewhere in the cell window and drag it
to create an active area. release the button when you're satisfied.
10. Press AL to unselect the active object.
11. Continue drawing the design by creating shapes in different layers
according to your design requirements.
You can try to copy the final layout in Figure 2 as an exercise. Remember
to follow carefully after the technology rules. As for dimensions, your
window is grided and the cursor is snapping to the grid points (by default).
The grid is exactly 1/2 lambda (half!!). You should explore the rest of
the editing functions like: COP+(copy), MVED+(Move Edge), FLI+(Flip), ROT(Rotate),
NOTC+(Notch), SLI+(Slice), MOV+(Move), and STR+(Stretch). These functions
can be a big help when you need to correct or replicate parts in your design.
Some of the functions are common to all Mentor applications. For example
you should know by now how to zoom out to get a bigger picture.
Figure 2
12. Save your work by doing: File > Cell > Save cell
Whenever you save the cell to disk, Mentor Graphics makes the cell immediately
available for others to use, and as a result, it has to change the cell
properties to read only. If you'll try to make a change to the cell now,
You'll notice that no changes are allowed. In order to make changes you
have to reserve the cell to yourself (and disable others from using it).
13. Reserve the cell by: File > Cell > Reserve
Now we need to assign port names to our inputs/outputs/power lines so ICGraph
could understand the connectivity between the schematic and the layout.
14. Select the VDD Rail (make sure only the rail is selected).
15. Click Connectivity > Port > Make port:
16. Use the arrows to select the port type (VDD and GND are power, the
rest are signals), the direction (in/out/bidi), and type in the port name
exactly as you defined it in the schematic (VERY IMPORTANT!!). Finally
click OK.
17. Define the rest of the ports (A,B,GND and Out).
18. Save your work.
The final stage in our project is the verification stage. In this stage
we will verify the correctness of our design in two steps. First we will
check if our design obeys the Mosis/AMI TinyChip technology rules. Second
we shell test our design against the schematic to see if our design conforms
with it.
1. If you are still inside the Expert Edit palette, Click Back and then
ICrules.
2. Click on Check and on OK in the dialog box.
ICRules is checking your design against Orbit's rules file. Observe the
status bar (the bar at the lowest part of ICStation's window). When the
check is over You'll see the remark: DRC completed. Read the number to
the right of Total Results: If it's 0, then you should probably apply for
a position in the Silicon Valley. In most cases you'll get some positive
number which is the number of errors DRC found in your design. Now you
have to go over each error, one by one, get back to Expert Edit, and correct
them.
3. Click on First.
A part of the screen will flash white, signaling you the error area. Read
the status bar, it will tell you the error's nature.
4. Click on Next.
The next error will show up.
5. Go back to Expert Edit and correct all the errors. Run DRC again.
6. Do step 5 until no more errors are reported.
We know now that our masks conform with the technology rules. The last
thing left to be checked is the correctness of the masks against the schematic.
The mask level LVS (ICtrace(M)) takes the design viewpoint that you've created in DVE and, using it, extracts from the schematic database two major parts. The first is an EDDM netlist. The netlist is a database describing the connectivity between the primitives in the design and the names of the I/O nets. The second is the primitive parameter list. This database describes the physical parameters of the primitives in the design (in our case the transistor's dimensions). LVS then starts a special algorithm which uses the I/O net names as anchors to map the schematic netlist into the masks database. LVS checks every schematic net against the masks and reports any discrepancies, then it checks out the primitive properties (in our case, the dimensions). If everything goes well, LVS prints at the top of the report a 'V' sign, a box with "CORRECT" in it, and a smiling face:
# ###################
_ _
#
# #
* *
# # #
CORRECT # |
# # #
# \___/
# ###################
and if, unfortunately, it finds errors we will get in the report:
# # #####################
# # #
#
# #
INCORRECT #
# #
#
#
# #
#####################
The report itself is very informative and contains valuable information
that will help you in debugging your masks. If you're getting an incorrect
report, study the error lists in the report carefully, and apply the corrections
to the masks. Except of the report LVS has a handful of tools to locate
the errors on the mask. We will not describe them here, but you should
explore them by yourself (they will make your work much easier). They are
all placed in the ICtrace(M) palette.
First we should setup LVS.
1. Click Back until you are in the IC_Palettes.
2. Click on ICtrace(M).
3. Click on LVS.
4. Click on the Navigator... Button under Source Name
(this is the viewpoint that LVS is going to use as data source).
You should see your "mynand" folder in the Navigator box.
5. Double click on the mynand folder.
You should see an lvs viewpoint object (marked with a small dv box
beside it).
6. Select the lvs viewpoint, and click OK in the Navigator box.
7. Click on Setup LVS...
8. In the Recognize Gates Click on No.
This is done to disable LVS from trying to analyze the masks at the logic
gate level (it only works for standard cell designs). We also need to
change the Ground name to be GND (not VSS).
9. Move the cursor over the VSS Ground name, and type GND to replace it.
10. Click OK in the Setup LVS box.
11. Click on Setup Trace Props...
The trace properties tell LVS which component properties to check against
the mask database. As you probably see, the default setup is not to check
any properties. We have entered the gate L/W properties and so we would
like LVS to trace them. Each transistor in the schematic has an absolute
length and absolute width properties. The absolute properties are the channel
length and width, expressed in meters (this is derived by multiplying the
length/width with lambda). We need to change the schematic property name
to be the absolute values. The related components are mn (MOS N-type) and
mp (MOS P-type), and for each we have an 'alength' property and a 'awidth'
property that we need to set:
12. Click on the no button in the topmost line of the box (the mn-w property
line), so it will turn to a yes.
13. Change the 'instpar(w)' on the 'Source Property Name' Column to 'awidth'
14. Do the same for the second (mp-width), fifth (mn-length), and sixth
(mp-length) lines, remembering to replace instpar(w) with awidth, and
instpar(l) with alength.
15. Click OK in the Setup Trace Properties dialog box.
16. Click OK in the LVS(Mask) dialog box.
LVS starts its checkout. You can follow its progress by watching the status
bar. When LVS finishes, the line Mask results database loaded appears.
We can now go to see LVS's report.
17. Click (left mouse) on the arrow beside Report.
18. Click (right mouse) on the [Report]LVS.
The report window will open up and a smiling face will grin at you (hopefully).
if it's not then you should read the report carefully (maybe write some
notes), go back to the mask window and to the Expert Edit palette, and
correct your errors. then do LVS again (this time you do not need to setup
anything in the LVS box - Just click LVS and OK).
Getting a correct LVS concludes this tutorial. You have a silicon mask that is fabricatable and conforms to the schematic. The only unverified part in it is the actual functionality of the electronics. Small size designs can be functionally-verified by using a switch level simulator (a simulator that can simulate the design in the transistor level). This method will not work for large designs because of the enormous amount of calculations needed for such a simulation. For those designs there are a few different methodologies which will be discussed later in class.
Written by: Matanya Elchanani
Please visit the VLSI home page of the University of Bridgeport