University of Bridgeport

School of Engineering and Design

Department of Computer Science and Engineering



Simulation of Full Custom NAND design
Using
Mentor Graphics

Introduction

This tutorial will give you a short introduction to the Mentor-Graphics Analog Simulation facilities, and guide you through the testing of the simple CMOS NAND gate you created previously. The tutorial assumes you have completed the full custom IC lab session successfuly, and you have the NAND gate design available. If you don't, please go back to the Full Custom IC Design tutorial, and complete it first. Simulation is a computational method that allows us to systematically predict the behaviour of a circuit or device based on a model. A simulation is as precise as the model that describes the behaviour of the device's primitivies. On the other hand, the more elaborate model, the more CPU intensive will the simualtion be. As a result, engineers are using different simulation techniques to simulate circuits of different sizes. The key issue in proper simulation of a design is hierarchy. Every design should start with a well difined set of primitives. To have the design properly simulated, a designer should have every primitive accompanied with a highly elaborate simulation model. The design process should begin by creating basic simple structures out of the primitives, those should be simulated accurately. After simulation, new "coarse grain" models should be created for those structures, and the rest of the design should be done with the latter.

Introduction to applications

In this lab, you will use one new product out of the Mentor-Graphics package.

Accusim
The Accusim application is a graphic front end and a post processor for SPICE like kernels. Currently it is attached to the ELDO SPICE kernel which is included with the Mentor-Graphics Analog-Station package. You will do all your analog simulation session in it.

Lets get to work!


Simulation setup

  • Invoke Accusim on our design by typing "accusim mynand/accusim" at the terminal.

    • You are now placed in the DC mode simulation. You should see your schematic design open in a window inside the simulator workspace. First, we have to load a model library for our parts. The model library you are going to load is an actual AMI05 SPICE model, that was statistically collected from a large fabrication run in AMI.

  • Click on Files > Auxiliary Files > Load Model Library...

  • In the dialog box, enter $UB_MODLIB/ami05.mod , then hit Ok

    • The library should load and we can start with a simple I/O simulation.

  • Select the "A" network by dragging a rectangle around the "A" port using your left mouse button.

    • We now have to define a "force" on this network, so we will be able to "force" it externally to any voltage we like.

  • Click [DC Mode] ADD FORCE. In the dialog box, set the Magnitude to 5, then press OK.

    • You should see a force probe (a circle with data in it) appear beside the forced nets on the schematic.

  • Do the same to the "B" network

    • Let's have some report windows available:

  • Click Report > Forces on Schematic
  • Click Report > Keeps > Schematic keeps

    • you should see our forces being displayed in the forces report.

  • Unselect all signals (F2), then select Net "A".

  • Click [DC Mode] SETUP ANALYSIS

  • Click on DC Sweep

  • Change the "from" value to 0, and the to value to "5".

    • Notice that the net name already has the "A" netlist that we would like to sweep between 0 and 5V.

  • Click OK

    • Notice that the simulation conditions have been updated in the simulation status window (upper left corner of the window). We now have to add keeps. Those are the circuit nodes that will be recorded by the simulator. Because our circuit is small we will keep all the nodes:

  • Click [DC Mode] ADD KEEPS

  • Click on ALL (the one at the top) and on OK.

    • You should see the Object "/" added to the Keeps report window (Accusim understands signal names as a hirarchy similar to a file system and so keeping "/" means keep everything from the signal tree root and down).

    Now, let's run a simulation

  • Click [DC Mode] RUN

    • The status window will show "RUNNING" for a few moments. Wait for the "NOT RUNNI NG" message to appear. We now need to view the results.

  • select the "A", "B" and "Out" networks.

  • Click on [RESULT] CHART

    • You should get the IN/OUT transfer function on your window. Move the cursor over the plot. You can read the exact values where the cursor stands on the upper left window corner. Does this plot agree with your knowledge of CMOS NAND gate?

  • Repeat the simulation, but this time, run the sweep on net "B" (you don't have to redefine any of the forces, just repeat the "Setup Analysis" with the "B" net selected. This will sweep net "B" instead of "A".

  • Close the chart window by clicking Close on the chart's window pooldown (click on the window's left button).

    • We will now generate a Time Domain simulation.

  • Click on TIME MODE

    • If this is the first time you launch a Time analysis you will get a setup window.

  • Check that the Transient button is pushed, the Time Step is 1N (1 nanosecond), and the Stop Time is 0.1U (100 Nanoseconds).

  • Click OK

    • delete all the previously defined forces by:

  • Delete > Forces... > All signals > OK

  • Select the "A" network and Click on ADD FORCE

  • Choose a PULSE Force type

  • Change the Pulsed Value to 5, Pulse Width to 30N, and the Period to 100N

  • Repeat the above for net "B", with a Pulse Width of 60N (the rest should be the same).

  • Click OK

  • Click [Time Mode] RUN

  • Select "A", "B" and "Out" networks, and Click [RESULT] TRACE

    • You should have an Analog Trace of the input signal and the resultant output. Does that output conform with your expectations from a NAND? If not, then what happened?

  • Close the Accusim window, and start design architect on your mynand design.

  • Add a load resistor between the Out port and GND. You can find the resistor the generic parts palette inside the MGC Analog Libraries.

  • Set the resistor value to be 3K (to do that, you'll need to change the INSTPAR property of the resistor).

  • Check and save your sheet.

  • Start Accusim on your revised design.

  • Repeat the I/O and time domain simulations you did previously on the loaded design.

    • Are there any differences, if yes - note what are the differences.

    Is the design working in a satisfactory manner? If not, can you suggest a solution (except, of course, changing the load resistor).

    The simulator allows you to change part properties in the schematic of the simulator. This way you can experimenet and optimize the design, without leaving the simulation environment. You can do that the same way you did it in Design Architect.

  • Try your solution in the simulator. Did your suggestion solve the problem?