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  Books

  1. Khaled Elleithy, Advances and Innovations in Systems, Computing Sciences and Software Engineering, Springer, June 2007.
  2. Tarek Sobh, Khaled Elleithy, Ausif Mahmood and Mohamed Karim, Innovative Algorithms and Techniques in Automation, Industrial Electronics and Telecommunications, Springer, June 2007.
  3. Khaled Elleithy, Tarek Sobh, Ausif Mahmood, Magued Iskander and Mohammad Karim, Advances in Computer, Information, and Systems Sciences, and Engineering: Proceedings of IETA 2005, TeNe 2005 and EIAE 2005, Springer, September 2006.
  4. Tarek Sobh and Khaled Elleithy, Advances in Systems, Computing Sciences and Software Engineering: Proceedings of SCSS 2005, Springer, September 2006.

  Book Chapters

  1. Aasia Riasat, Syed S. Rizvi, Khaled M. Elleithy, Farheen Zehara, and Faraz Arain, "The Role of System Dynamics in Learning Environments, "International Conference on Engineering Education,Instructional Technology, Assessment, and E-learning (EIAE 07), Bridgeport, CT, USA. December 3 - 12, 2007. (Audio Presentation)
  2. Syed S. Rizvi, Khaled M. Elleithy, Khushboo Patel, and Chaitali Patel, "Use of Self-Adaptive Methodology in Wireless Sensor Networks for Reducing the Energy Consumption", International Conference on Telecommunications and Networking (TeNe 07), Bridgeport, CT, USA. December 3 - 12, 2007. (Audio Presentation)
  3. Syed S. Rizvi, Aasia Riasat, Muhammad S. Rashid, and Khaled M. Elleithy, "Bandwidth Problem in High Performance Packet Switching Network," International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering (CISSE 07), Bridgeport, CT, USA. December 3 - 12, 2007. (Audio Presentation)
  4. Syed S. Rizvi, Aasia Riasat, Muhammad S. Rashid, and Khaled M. Elleithy, "An Efficient Scheme for Traffic Management in ATM Networks," International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering (CISSE 07), Bridgeport, CT, USA. December 3 - 12, 2007. (Audio Presentation)
  5. Ajay Shrestha, Khaled M. Elleithy, and Syed S. Rizvi, "Investigating the effects of Encoder Schemes, WFQ & SAD on VoIP QoS," International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering (CISSE 07), Bridgeport, CT, USA. December 3 - 12, 2007. (Audio Presentation)
  6. Aasia Riasat, Syed S. Rizvi, Khaled M. Elleithy, Faraz Arain, Rizwan M. Qureshi, "Dynamic Semantics of the Web: Useful Toll for the New Generation Agent-Based Software," International Conference on Engineering Education, Instructional Technology, Assessment, and E-learning (EIAE 07), Bridgeport, CT, USA. December 3 - 12, 2007. (Audio Presentation)
  7. Khurram M. Rajput, Khaled M. Elleithy, and Syed S. Rizvi, "A Novel Approach for Creating Consistent Trust and Cooperation (CTC) among Mobile Nodes of Ad Hoc Network," International Conference on Telecommunications and Networking (TeNe 07), Bridgeport, CT, USA. December 3 - 12, 2007.
  8. Syed S. Rizvi, K. M. Elleithy, Aasia Riasat, "Minimizing the Null Message Exchange in Conservative Distributed Simulation," Book Chapter, Innovative Algorithms and Techniques in Automation, Industrial Electronics and Telecommunications, Springer, June 2007.
  9. K. M. Elleithy and I. Rimawi, "Design, Analysis and Implementation of a Cyber Vote System." Book Chapter, Advances in Computer, Information, and Systems Sciences, and Engineering: Proceedings of IETA 2005, TeNe 2005 and EIAE 2005, Springer, September 2006.

  Journal Publications

  1. Sobh, K. Elleithy and S. Patel, "Reverse Engineering of VLSI Chips: A Roadmap,'' In the Journal of Engineering and Applied Sciences, Volume 2, number 2, pp 290-298, 2007.
  2. K. M. Elleithy, D. Blagovic, W. Cheng, and P. Sideleau "Implementation and Comparison of Denial Of Service Attack Techniques", Journal of Systemics, Cybernetics and Informatics, Volume 3, Number 1, 2006.
  3. K. M. Elleithy, "Formal Verification of Systems On Chip: Current & Future Directions," System on Chip for Realtime Systems, W. Badawy and G. Jullian, editors, Kluwewr Academic Publishing, Fall 2003.
  4. Elleithy, K. and Sobh, Tarek M., "A Framework for Reverse Engineering VLSI Chips." In Intelligent Systems and Signal Processing, Elsevier Science, 2003.
  5. K. M. Elelithy, A. Sing, T. Narayanan, N. Bhalla, L. Al-Rashid, BlueDArt: Radition Data Collection and Warning System," Journal of Internet Technology, July 2003.
  6. K. M. Elleithy, H. Ha, S. Karki, A. Kaulgud, U. Rana,  "An Algorithm to the IMT2000 Power Control," Journal of Internet Technology, July 2003.
  7. K. M. Elleithy and Rama C. Reddy, "Comparison of Firewalls Security and Performance Issues," Journal of Internet Technology, April 2002.
  8. Sobh and K. Elleithy, "Internet-Based Robotics and Automation." In the International Journal of Robotics & Automation, special issue on Web-based Automation, volume 17, Number 3, 103-105, 2002.
  9. K. M. Elleithy and A. Komaralingam, "Automation and Management of Mobile Content ," International Journal of Robotics and Automation, November 2002.
  10. K. M. Elleithy, and A. A. Amin, "Mapping CIRCAL based Algorithms to Event Logic," The Journal of University of Kuwait, Topical issue No. 1, pp. 27-42, Dec. 1996.
  11. S. M. Sait, K. M. Elleithy, and M. Hassan, "Formal Synthesis of VLSI Layouts from Algorithmic Specifications," Computer Systems Science and Engineering, vol. 11, No. 2, pp. 67-81, March 1996.
  12. K. M. Elleithy, and M. A. Bayoumi, "A Systolic Architecture for Modulo Multiplication," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 42, no. 11, pp. 725-729, Nov. 1995.
  13. K. M. Elleithy and M. A. Bayoumi, "Fast and Flexible Architectures for RNS Arithmetic Decoding," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, no. 4, pp. 226-235, April 1992.
  14. K. M. Elleithy, M. A. Bayoumi and L. M. Delcambre, "VLSI Implementation of A Systolic Database Machine," Integration the VLSI Journal, No. 11, pp. 169-190, Nov. 1991.
  15. K. M. Elleithy and M. A. Bayoumi, "A   Algorithm for modulo Addition," IEEE Transactions on Circuits and Systems, vol. 37, no. 5, pp. 628-631, May 1990.

  Conference Publications

  1. Auf Akhtar, Syed S. Rizvi, and Khaled M. Elleithy, "A Novel Approach of Using Data Guard for Disaster Recovery & Rolling Upgrades," ASEE Zone I Conference 2008, United State Military Academy, West Point, NY March 28 - 29.
  2. Syed S. Rizvi, Khaled M. Elleithy, and Aasia Riasat, "SNR Analysis of a Low-Complexity Wireless Multiuser Receiver for DS-CDMA Systems," IEEE International Symposium on Wireless Pervasive Computing (IEEE ISWPC-08) 2008, 7 - 9 May 2008 Santorini, Greece.
  3. Syed S. Rizvi, Khaled M. Elleithy, and Aasia Riasat, "Transformation Matrix System for Reducing the Computational Complexity of Wireless Multi-user Receivers for DS-CDMA Systems," 5th International Conference on Information Technology: New Generations ITNG 2008, April 7-9, 2008, Las Vegas, Nevada, USA.
  4. Syed S. Rizvi, Khaled M. Elleithy, and Aasia Riasat, "A New Mathematical Model for Optimizing the Performance of Parallel and Discrete Event Simulation Systems," 11th Communications and Networking Simulation Symposium (CNS'08), Part of the 2008 Spring Simulation Multiconference (SpringSim'08). April 14-16, 2008. Crowne Plaza Ottawa, Ottawa, Ontario
  5. Syed S. Rizvi, Khaled M. Elleithy, and Aasia Riasat, "Deterministic Formalization of the Processing Gain for Reducing MAI in Wireless Multiuser DS-CDMA Systems," 5th Annual IEEE Consumer Communications and Networking Conference (IEEE CCNC'2008), pp. 859 - 860, Las Vegas, Nevada January 10 - 12, 2008.
  6. Syed S. Rizvi, Khaled M. Elleithy, and Aasia Riasat, "Use of Processing Gain to  Suppress Multi Access Interference (MAI) in CDMA Based Multiuser Receiver," International Wireless communications and Mobile Computing Conference 2007 (IWCMC 2007), Honolulu, Hawaii, August 12-16, 2007.
  7. Syed S. Rizvi, Khaled M. Elleithy, and Aasia Riasat, "Trees and Butterflies Barriers in Distributed Simulation System: A Better Approach to Improve Latency and the Processor Idle Time", IEEE International Conference on Information and Emerging Technologies (IEEE ICIET-2007), pp. 1 - 6, July 06-07, 2007, Karachi, Pakistan.
  8. Syed S. Rizvi, Khaled M. Elleithy, and Aasia Riasat, "The Impact of Reduced Computational Complexity of Multiuser Detectors on the Processing Gain in a Wireless DS-CDMA Multiuser System," Proceedings of the 2007 International Conference on Wireless Networks (ICWN'07). Part of the 2007 World Congress in Computer Science, Computer Engineering, & Applied Computing (Worldcomp'07), pp. 70 - 76, Las Vegas, Nevada, USA, June 25-28, 2007.
  9. Syed S. Rizvi, K. M. Elleithy, and Aasia Riasat, "Transformation Matrix Algorithm for Reducing the Computational Complexity of Multiuser Receivers for DS-CDMA Wireless Systems," Wireless Telecommunication Symposium (WTS 2007), Pomona, California, April 26-28 2007.
  10. K. M. Elleithy and A. Maqbool, "Implementations of Location Awareness Technologies and their Applications" Wireless Telecommunication Symposium (WTS 2007), Pomona, California, April 26-28 2007.
  11. Khushboo Patel, Chaitali Patel, Syed S. Rizvi, and Khaled M. Elleithy, "An Approach to Reduce the Energy Consumption in Wireless Sensor Networks through Active Nodes Optimization," 2007 Nefor Engineering Education Confernce, April 20-21, 2007.
  12. Syed S. Rizvi, K. M. Elleithy, Aasia Riasat, "Minimizing the Null Message Exchange in Conservative Distributed Simulation," International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering, CISSE 2006, pp. 443-448 ,December 4-14, Bridgeport CT, 2006. ( Audio Presentation)
  13. K. M. Elleithy and I. Rimawi, Design, Analysis and Implementation of a Cyber Vote System, International Joint Conferences, on Computer, Information, and Systems Sciences, and Engineering, (CIS2E 05), 10 - 20 December 2005, Virtual Conference.
  14. K. M. Elleithy, D. Blagovic, W. Cheng, and P. Sideleau "Implementation and Comparison Of Denial Of Service Attack Techniques", the 8th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2004), Orlando, USA, July 18-21, 2004.
  15. K. M. Elleithy, S. Bell, B. Plaag, and D. Stone, "Implementation and Comparison of a Rules-Based Approach and a Statistical Approach Intrusion Detection Systems" I2TS'2003, 2nd International Information and Telecommunication, Technologies Symposium. Florian™çßolis, Brazil - Nov 26-29, 2003.
  16. K. M. Elleithy and T. M. Sobh, "A Framework for Reverse Engineering VLSI Chips," IFAC Conference on Intelligent Control and Signal Processing, Portugal, April 2003.
  17. K. M. Elleithy, A. Adebola, S. Shrestha , and B. Bhattarai,  "Support of a Banking System Using WAP," The 6th World Multiconference on systemics, cybernetics, and Informatics, Orlando, USA, July 14-18, 2002.
  18. K. M. Elleithy, H. Ha Hyungate, K. Amol, R. Utpal, "Simulation and Improvement of IMT2000 Power Control," The 6th World Multiconference on systemics, cybernetics, and Informatics, Orlando, USA, July 14-18, 2002.
  19. K. M. Elleithy, ""Formal Verification of Systems On Chip: Current & Future Directions," invited paper, 2002 International Workshop on System-on-Chip for Real-Time Applications, Banff, Canada, July 6-7, 2002.
  20. K. M. Elleithy and A. Komaralingam, "A Mobile Content Manager," International Conference on Industrial Electronics, Technology and Automation IETA2001, Cairo, Egypt, 19-21 December.
  21. K. M. Elleithy and K.  Al-Utaibi, "Performance Analysis of a Priority Traffic Shaper for ATM Networks," Applied Telecommunication Symposium, Seattle, Washington, April 22 -26, 2001
  22. K. M. Elleithy & A. Al-Suwaiyan, "Network Traffic Characterization for high-speed networks supporting multimedia," 34th Annual Simulation Symposium, Seattle, Washington, April 22-26, 2001.
  23. K. M. Elleithy and M. I. Khan "Security in Internet Payment System and Queuing Network Analysis " International Conference on Advances in Infrastructure for Electronic Business, Science, and Education on the Internet, Rome, Italy, August 2000. (Invited paper)
  24. K. M. Elleithy & Alaa A. Amin, "Area Estimation for DSP Algorithms," IEEE Workshop on SiGNAL PROCESSING SYSTEMS (SiPS) Design and Implementation, Lafayette, Louisiana, October 11-13, 2000.
  25. K. M. Elleithy, "A Genetic Algorithm for Register Allocation" 9th great Lake Symposium on VLSI, Michigan, March 1999.
  26. K. M. Elleithy and E. G. AbdelFattah, "A Simulated Annealing Algorithm for Register Allocation," Fifth Saudi Engineering Conference, pp. 373-382, March 1999
  27. M. A. Aref and K. M. Elleithy, "HOOVER: Hardware Object-Oriented Verification," 8th Great Lake Symposium on VLSI, GLS'98, Lafayette, Louisiana, Feb. 1998.
  28. K. M. Elleithy and E. G. Abd-El-Fattah, "New Non-deterministic Approaches for Register Allocation," 4th IEEE International Conference on Electronics, Circuits, and Systems, Cairo, Dec. 1997.
  29. K. M. Elleithy, and S. H. Abdul-Jauwad, "A Transputer Based Sonar Range finding," The Journal of The Faculty of Science, United Arab Emirates University, May 1997, pp. 100-108.
  30. A. Amin and K. M. Elleithy, "Self Timing of Event Logic Data-Paths," The Eighth International Conference on Microelectronics, Cairo, Dec. 1996.
  31. K. M. Elleithy and M. A. Aref, "Verification Strategy in Prover," The Asia Pacific Conference on Circuits and Systems, Seoul, Korea, Nov. 18-21, 1996.
  32. K. M. Elleithy, "Choosing System Moduli for RNS Arithmetic Processors," 30th Annual Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, Nov. 3-6, 1996.
  33. Amin and K. M. Elleithy, "Mapping CIRCAL based Algorithms to Event Logic using a Standard Cell Library," The Seventh International Conference on Microelectronics, Kuala Lumpur, Dec. 19-21, 1995.
  34. K. M. Elleithy and A. A. Amin, "Synthesizing Digital Signal Processing Algorithms from Formal Descriptions," The Sixth International Conference on Signal Processing Applications and Technology, Boston, pp. 901-905, Oct. 24-26, 1995.
  35. K. M. Elleithy and A. A. Amin, "An Event Logic Architecture for CIRCAL Algorithms," The Seventh IASTED International Conference on Parallel and Distributed Computing and Systems, Washington, D. C., pp. 311-314, Oct. 18-21, 1995.
  36. K. M. Elleithy and A. A. Amin, "A Formal Approach for Synthesizing Digital Signal Processing Algorithms," IEEE Singapore International Conference on Signal Processing, Circuits and Systems, Singapore, pp. 163-168, July 3-7, 1995.
  37. K. M. Elleithy, "An Integer Programming Approach for Choosing the System Moduli for RNS Processor," Minisymposium on Optimization Theory and Applications, KFUPM, Dhahran, May 30, 1995.
  38. K. M. Elleithy, "Formal Verification of DSP VLSI Architectures," International Conference on Electronics, Circuits and Systems, Cairo, Egypt, Dec. 19-22, 1994.
  39. K. M. Elleithy and M. A. Al-Humaigani, "Formal Environments for Parallel Hardware Description Languages," International Conference on Electronics, Circuits and Systems, Cairo, Egypt, pp. 440-445, Dec. 19-22, 1994.
  40. K. M. Elleithy and M. A. Al-Humaigani,  "Parallelism Analysis and Extraction of Digital Signal Processing Algorithms," Twenty-Eighth Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, pp. 1041-1045, Oct. 31-Nov. 2, 1994.
  41. Maruf and K. M. Elleithy, "RISC Support for Real-Time Features," Sixth International Conference on Microelectronics, Istanbul, Turkey, Sep. 5-7, 1994.
  42. K. M. Elleithy and M. A. Al-Humaigani, "Formal Verification of DSP VLSI Architectures: A Tutorial" 37th Midwest Symposium on Circuits and Systems, Lafayette, Louisiana, pp. 351-355, August 3-5, 1994.
  43. K. M. Elleithy and M. A. Aref, "A Rule-based Approach for High Speed Adders Design Verification," 37th Midwest Symposium on Circuits and Systems, Lafayette, Louisiana, pp. 274-277, August 3-5, 1994.
  44. K. M. Elleithy, Samir H. Abdul-Jauwad, and Jafar Al-Rashed, "A Transputer Based Sonar Range finding," Workshop on Optimization and Parallel Computation, Al-Ain, United Arab Emirates, May 8-11, 1994.
  45. K. M. Elleithy and Muhammed A. Al-Humaigani, "A Characteristic Model for Formal Parallel Hardware Description Languages," Workshop on Optimization and Parallel Computation, Al-Ain, United Arab Emirates, May 8-11, 1994.
  46. S. M. Sait, M. Hasan, and K. M. Elleithy, "Design of a cell Library for Formal High Level Synthesis," Mediterranean Electrontecnical Conference Melecon 94, April 1994.
  47. K. M. Elleithy, Sadiq M. Sait and Masud-ul-Hasaan,  "Formal Design of VLSI Systems," Fifth International Conference on Microelectronics, Dhahran, pp. 214-219, Dec. 1993.
  48. K. M. Elleithy, "Formal Hardware Verification of VLSI Architecture Current Status and Future Directions," Fifth International Conference on Microelectronics, Dhahran, pp. 197-201, Dec. 1993.
  49. M. A. Aref and K. M. Elleithy, "PROVER: A Production System for Formal Hardware Verification," Fifth International Conference on Microelectronics, Dhahran, pp. 210-213, Dec. 1993
  50. K. M. Elleithy and Mostafa A. Aref,  "A Production Based System for Formal Verification of Digital Signal Processing Architectures," Twenty-Seventh Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, pp. 1618-1622, Nov. 1-3, 1993.
  51. K. M. Elleithy and Adel Al-Massarani, "PLORA: A Prolog and LISP oriented RISC Architecture," 18th International Conference for Statistics and Computer Science and its Scientific and Social Applications, Egypt, April 1993.
  52. K. M. Elleithy, "Systolic Arithmetic Architectures," Fifth International Conference on VLSI Design, Bangalore, India, January 1992.
  53. K. M. Elleithy and M. A. Bayoumi, "A Massively Parallel RNS Architecture," Twenty Fifth Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, pp. 408-412, November 1991.
  54. K. M. Elleithy and M. A. Bayoumi, "Formal Design of RNS Processors," Proc. of the International Conference on Circuits and Systems, pp. 605-608, China, June 1991.
  55. K. M. Elleithy and M. A. Bayoumi, "From Algorithms to Parallel architectures: A Formal Approach," Proc. of Fifth International Symposium on Parallel Processing, pp. 358-363, April 1991.
  56. K. M. Elleithy and M. A. Bayoumi, "Formalization of DSP Architectural Synthesis," Proc. of the Fifth European Signal Processing Conference, Spain, pp. 1451-1454, vol. 3., Sep. 1990.
  57. K. M. Elleithy and M. A. Bayoumi, "A Formal Design Methodology for Parallel Architectures," Proc. of the International Conference on Application Specific Array Processors, pp. 603-614, Sep. 1990.
  58. K. M. Elleithy and M. A. Bayoumi, "Formal Synthesis of Parallel Architectures from Recursive Equations," Proc. of the 1990 International Conference on Parallel Processing, vol. I, pp. 145-148, Aug. 1990.
  59. K. M. Elleithy and M. A. Bayoumi, "Synthesizing DSP Architectures from Behavioral Specifications: A Formal Approach," Proc. of the 1990 IEEE International Symposium for Circuits and Systems, pp. 1131-1134, May 1990.
  60. K. M. Elleithy and M. A. Bayoumi, "A Formal High Level Synthesis Approach for DSP Architectures," Proc. of the 1990 International Conf. on Acoustics, Speech and Signal Processing, pp. 897-900, April 1990.
  61. K. M. Elleithy and M. A. Bayoumi, "A Formal Framework for Synthesis of Parallel Architectures," Proc. of the Fourth Annual Symposium on Parallel Processing, April 1990.
  62. K. M. Elleithy and M. A. Bayoumi, "A Framework for High Level Synthesis of Digital Architectures from U-recursive Algorithms," Proc. of the ACM Eighteenth Annual Computer Science Conference, pp. 305-311, Feb. 1990.
  63. K. M. Elleithy, M. A. Bayoumi, and K. P. Lee, "  Architectures for RNS Arithmetic Decoding," Proc. of the 9th Symposium on Computer Arithmetic, pp. 202-209, Sep. 1989.
  64. K. M. Elleithy and M. A. Bayoumi, "A   Algorithm for Modulo Multiplication," Proc. of the 32nd Midwest Symposium on Circuits and Systems, pp. 353-356, Aug. 1989.
  65. P. Lee, M. A. Bayoumi and K. M. Elleithy, "A Fast and Flexible Residue Decoder Based on the Chinese Remainder Theorem," Proc. of The 1989 International Symposium on Circuits and Systems, pp. 200-203, May 1989.
  66. K. M. Elleithy, M. A. Bayoumi, and L. M. Delcambre, "A Systolic Machine for Relational Database and Hashing," Proc. Third Annual Parallel Processing Symposium, pp. 621-635, Mar. 1989.
  67. M. A. Bayoumi and K. M. Elleithy, "A Logic Programming Approach for DSP architectures Design," Proc. of the 22nd IEEE Asilomar Conf. on Signals, Systems and Computers, vol. 2, pp. 753-757, Nov. 1988.
  68. N. El-Derini, K. M. Elleithy, and E. G. Mohammed, "Implementation and Analysis of a Bilinear Multiplier," Faculty of Engineering Research Journal, Alexandria University, Vol. 12, 1983.

  Reports

  1. K. M. Elleithy and Tarek Sobh, "Wireless LAN Laboratory," National Sceinec Foundation (NSF), Proposal, June 2001.
  2. K. M. Elleithy, "Mobile Content Mnanger," United Nations Develoment Program (UNDP), Transfer of Knowledge through Expatriate Nationals (TOTKEN), Proposal, July 2001.
  3. M. A Aref, K. M. Elleithy, T. Sobh,  "Developing an Intelligence Web Based Expert System for Anemia Diagnosis and Categorization''U.S. Egypt Joint Board on Scientific and Technological Cooperation, Proposal, October 2001.
  4. K. Altawil and K. Elleithy, "Security Implementation and Evaluation of Armco Enterprise Network," Saudi Aramco, Final report, May 2000.
  5. K. Altawil and K. Elleithy, "Security Implementation and Evaluation of Armco Enterprise Network," Saudi Aramco, First report, May 1999.
  6. K. Altawil and K. Elleithy, "Security Implementation and Evaluation of Armco Enterprise Network," Saudi Aramco, Proposal, January 1999.
  7. K. M. Elleithy and A. A. Amin, "A Formal Methodology for Parallel VLSI Algorithm Design," King Abdulaziz City of Science and Technology, Final report, AR-13-11, March 1996.
  8. K. M. Elleithy and A. A. Amin, "A Formal Methodology for Parallel VLSI Algorithm Design," King Abdulaziz City of Science and Technology, progress report #5, AR-13-11, June 1995.
  9. K. M. Elleithy and A. A. Amin, "A Formal Methodology for Parallel VLSI Algorithm Design," King Abdulaziz City of Science and Technology, progress report #4, AR-13-11, January 1995.
  10. K. M. Elleithy and A. A. Amin, "A Formal Methodology for Parallel VLSI Algorithm Design," King Abdulaziz City of Science and Technology, progress report #3, AR-13-11, June 1994.
  11. K. M. Elleithy and M. A. Aref, "A Production System Based Environment for Formal Hardware Verification," King Abdulaziz City of Science and Technology, proposal report, AR-15-63, January 1994.
  12. M. A. Barr, M. Y. Osman, S. H. Juwad, S. M. Sait, M. S. Benten, and K. M. Elleithy, "An Integrated Framework for Synthesis, Verification, Optimization, and Testability of VLSI-Based Design," King Abdulaziz City of Science and Technology, proposal report, AR-15-74, January 1994.
  13. K. M. Elleithy and A. A. Amin, "A Formal Methodology for Parallel VLSI Algorithm Design," King Abdulaziz City of Science and Technology, progress report #2, AR-13-11, January 1994.
  14. K. M. Elleithy and A. A. Amin, "A Formal Methodology for Parallel VLSI Algorithm Design," King Abdulaziz City of Science and Technology, progress report #1, AR-13-11, July 1993.
  15. K. M. Elleithy and A. A. Amin, "A Formal Methodology for Parallel VLSI Algorithm Design," King Abdulaziz City of Science and Technology, proposal report, AR-13-11, July 1991.
  16. K. M. Elleithy, "Formalization of High Level Synthesis," VLSI Technical Report TR 89-8-2, The Center for Advanced Computer Studies, University of Southwestern Louisiana, 1989.
  17. K. M. Elleithy, "Optimization of SQL queries" The Center for Advanced Computer Studies, University of South Western Louisiana, Project Report, May 88.
  18. K. M. Elleithy, "Emulating the Instruction Set of a Simple Computer," The Center for Advanced Computer Studies, University of South Western Louisiana, Project Report, December 1987.
  19. K. M. Elleithy, "On bit-Parallel Implementation for the Chinese Remainder Theorem," VLSI Technical Report TR 87-8-1, The Center for Advanced Computer Studies, University of Southwestern Louisiana, 1987.
  20. K. M. Elleithy, "Parallel Implementation of Searching Algorithms," The Center for Advanced Computer Studies, University of South Western Louisiana, project report, May 1987.
  21. K. M. Elleithy, "Parallel Implementation of Template Matching Algorithms," The Center for Advanced Computer Studies, University of South Western Louisiana, project report, May 1987.
  22. K. M. Elleithy, "A Library for Scene Analysis and Image processing," The Center for Advanced Computer Studies, University of South Western Louisiana, project report, April 1987.
  23. K. M. Elleithy, "On bit-Parallel Processing for Modulo Arithmetic," VLSI Technical Report TR 86-8-1, The Center for Advanced Computer Studies, University of Southwestern Louisiana, 1986.
  24. K. M. Elleithy, "Simulation of a Computer Queuing Model,'" The Center for Advanced Computer Studies, University of South Western Louisiana, project report, November 1986.
  25. K. M. Elleithy, "Design and Implementation of Switching Functions Representation and Minimization Package," The Center for Advanced Computer Studies, University of South Western Louisiana, project report, November 1986.

  Presentations in Conferences, Meetings, and Seminars

  1. "Transformation Matrix Algorithm for Reducing the Computational Complexity of Multiuser Receivers for DS-CDMA Wireless Systems," Wireless Telecommunication Symposium (WTS 2007), Pomona, California, April 26-28, 2007.
  2. "Implementations of Location Awareness Technologies and their Applications" Wireless Telecommunication Symposium (WTS 2007), Pomona, California, April 26-28, 2007.
  3. "Implementation and Comparison Of Denial Of Service Attack Techniques", the 8th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2004), Orlando, USA, July 18-21, 2004.
  4. "A Framework for Reverse Engineering VLSI Chips," IFAC Conference on Intelligent Control and Signal Processing, Portugal, April 2003.
  5. "Support of a Banking System Using WAP," The 6th World Multiconference on systemics, cybernetics, and Informatics, Orlando, USA, July 14-18, 2002.
  6. "Simulation and Improvement of IMT2000 Power Control," The 6th World Multiconference on systemics, cybernetics, and Informatics, Orlando, USA, July 14-18, 2002.
  7. "E-commerce" Public Lecture organized by Royal Commission at Jubail, Saudi Arabia, Dec. 1999.
  8. " Area Estimation for DSP Algorithms," IEEE Workshop on SiGNAL PROCESSING SYSTEMS (SiPS) Design and Implementation, Lafayette, Louisiana, October 11-13, 2000.
  9. "E-commerce" Saudi Internet 98 Meeting, Riyadh, Dec. 5-7, 1999
  10. "A Genetic Algorithm for Register Allocation" 9th great lake Symposium on VLSI, Michigan, March 1999.
  11. "A Simulated Annealing Algorithm for Register Allocation," Fifth Saudi Engineering Conference, March 1999
  12. "Net Security" Information Technology Center Internal Seminar for ITC Staff, Dhahran, Saudi Arabia, Nov. 1998.
  13. "Internet/Intranet for Business" Dhahran 15th Annual Computer, Communication & Office Technology Exhibition, Oct. 17-22, 1998.
  14. "HOOVER: Hardware Object-Oriented Verification," 8th Great Lake Symposium on VLSI, GLS'98, Lafayette, Louisiana, Feb. 1998.
  15. "New Non-deterministic Approaches for Register Allocation," 4th IEEE International Conference on Electronics, Circuits, and Systems, Cairo, Dec. 1997.
  16. "HOOVER: Hardware Object-Oriented Verification," 8th Great Lake Symposium on VLSI, GLS'98, Lafayette, Louisiana, Feb. 1998.
  17. "Electronic Commerce," Annual Computer Exhibition, KFUPM, April 1997.
  18. "Formal Hardware Verification," ICS/COE Fall Seminar Series, KFUPM, Dec. 1996.
  19. "Choosing System Moduli in RNS," ICS/COE Fall Seminar Series, Nov. 1996.
  20. "Choosing System Moduli for RNS Arithmetic Processors," 30th Annual Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, Nov. 3-6, 1996.
  21. "Synthesis of Digital Signal Processing Algorithms from Formal Descriptions," The Sixth International Conference on Signal Processing Applications and Technology, Boston, Oct. 24-26, 1995.
  22. "An Event Logic Architecture for CIRCAL Algorithms," The Seventh IASTED International Conference on Parallel and Distributed Computing and Systems, Washington, D. C., Oct. 18-21, 1995.
  23. "An Integer Programming Approach for Choosing the System Moduli for RNS Processor," Minisymposium on Optimization Theory and Applications, KFUPM, Dhahran, May 30, 1995.
  24. "Formal Verification of DSP VLSI Architectures," International Conference on Electronics, Circuits and Systems, Cairo, Egypt, Dec. 19-22, 1994.
  25. "Formal Environments for Parallel Hardware Description Languages," International Conference on Electronics, Circuits and Systems, Cairo, Egypt, Dec. 19-22, 1994.
  26. "Formal Verification of DSP VLSI Architectures: A Tutorial" 37th Midwest Symposium on Circuits and Systems, Lafayette, Louisiana, August 3-5, 1994.
  27. "A Rule-based Approach for High Speed Adders Design Verification," 37th Midwest Symposium on Circuits and Systems, Lafayette, Louisiana, August 3-5, 1994.
  28. "A Transputer Based Sonar Range finding," Workshop on Optimization and Parallel Computation, Al-Ain, United Arab Emirates, May 8-11, 1994.
  29. "A Characteristic Model for Formal Parallel Hardware Description Languages," Workshop on Optimization and Parallel Computation, Al-Ain, United Arab Emirates, May 8-11, 1994.
  30. "Formal Hardware Verification of VLSI Architecture Current Status and Future Directions," Fifth International Conference on Microelectronics, Dhahran, Saudi Arabia, Dec. 1993.
  31. "A Production Based System for Formal Verification of Digital Signal Processing Architectures," Twenty-Seventh Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, Nov. 1993.
  32. "PLORA: A Prolog and LISP oriented RISC Architecture," EinShams University, Cairo, April 1993.
  33. "RISC Architectures," Information & Computer Science Department Spring Lecture Series, King Fahd University, May 1992.
  34. "Foundations of Hardware Design Correctness," Computer Engineering Department, King Fahd University, December 1991.
  35. "A Massively Parallel RNS Architecture," 25th Asilomar Conference on Circuit and Systems, Pacific Grove, California, Nov. 1991.
  36. "Formal High Level Synthesis," Computer Engineering Department, King Fahd University, December 1990.
  37. "Synthesizing DSP Architectures from Behavioral Specifications: A Formal Approach," 1990 IEEE International Symposium for Circuits and Systems, New Orleans, May 1990.
  38. "Formalizing Behavioral Specifications Synthesis," Louisiana State University, Louisiana, April 1990.
  39. "A Framework for High Level Synthesis of Digital Architectures from U-recursive Algorithms," ACM Eighteenth Annual Computer Science Conference, Washington D. C., Feb. 1990.
  40. "Efficient Implementations of the Chinese Remainder Theorem," Computer Science and Automatic Control Department, Alexandria University, July 1989.
  41. "A Systolic Machine for Relational Database and Hashing," Third Annual Parallel Processing Symposium, Los Angles, Mar. 1989.
  42. "Residue Arithmetic: Parallelism at the Algorithmic Level," The Center for Advanced Computer Studies, University of Southwestern Louisiana, November 1987.